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Programmable Synchronous DC/DC Converter, Dual LDO Controller
POWER MANAGEMENT Description
The SC1185 combines a synchronous voltage mode controller with two low-dropout linear regulators providing most of the circuitry necessary to implement three DC/ DC converters for powering advanced microprocessors such as Pentium(R) II . The SC1185 switching section features an integrated 5 bit D/A converter, pulse by pulse current limiting, integrated power good signaling, and logic compatible shutdown. The SC1185 switching section operates at a fixed frequency of 140kHz, providing an optimum compromise between size, efficiency and cost in the intended application areas. The integrated D/A converter provides programmability of output voltage from 2.0V to 3.5V in 100mV increments and 1.30V to 2.05V in 50mV increments with no external components. The SC1185 linear sections are low dropout regulators supplying 1.5V for GTL bus and 2.5V for non-GTL I/O. The Reference voltage is made available for external linear regulators.
SC1185 & SC1185A
Features
Synchronous design, enables no heatsink solution 95% efficiency (switching section) 5 bit DAC for output programmability On chip power good function Designed for Intel Pentium(R) ll requirements 1.5V, 2.5V @ 1.25% for linear section 1.265V 1.5% Reference available 24-lead SO package. Lead free option available. Lead free product is fully WEEE and RoHS compliant.
Applications
Pentium(R) ll microprocessor supplies Flexible motherboards 1.3V to 3.5V microprocessor supplies Programmable triple power supplies
Typical Application Circuit
12V
5V
+
4.7uF
+ 1500uF
x4
10
0.1uF
0.1uF PWRGOOD VID0 VID1 VID2 VID3 VID4 EN
5 7 22 21 20 19 18 16 1 23 24 4
VCC PWRGOOD VID0 VID1 VID2 VID3 VID4 EN AGND LDOV GATE2 LDOS2
CS+ CS-
9 8 0.1uF IRLR3103N 1.00k 5mOhm 1.9uH 2.32k
17 VOSENSE
BSTH DH BSTL DL PGNDH PGNDL REF GATE1 LDOS1
15 11 14 13 10 12 6 2 3 12V 2R2 2R2 IRLR3103N
VCC_CORE
+
0.1uF
1k 3.3V
1500uF
x6
SC1185CS 3.3V 3 2 + 330uF IRLR024N + 330uF 330uF +
1.5V 2.5V
8 + 4
1 LM358
IRLR024N VLIN3 + 330uF
IRLR024N
Revision: July 28, 2005
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SC1185 & SC1185A
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.
Parameter VCC to GND PGND to GND BST to GND Operating Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec. Thermal Impedance Junction to Ambient Thermal Impedance Junction to Case
Symbol VIN
Maximum -0.3 to +7 +1 -0.3 to +15
Units V V V C C C C C/W C/W
TA TJ TSTG TL JA JC
0 to +70 0 to +125 -65 to +150 300 80 25
Electrical Characteristics
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70C
Parameter Switching Section Output Voltage Supply Voltage Supply Current Load Regulation Line Regulation Current Limit Voltage Oscillator Frequency Oscillator Max Duty Cycle Peak DH Sink/Source Current Peak DL Sink/Source Current Gain (AOL) VID Source Current VID Leakage Power good threshold voltage Dead time
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Conditions
Min
Typ
Max
Units
IO = 2A in Application Circuit VCC VCC = 5.0V IO = 0.8A to 15A
See Output Voltage Table 4.5 8 1 +0.15 60 125 90 70 140 95 85 160 7 15 V mA % % mV kHz % A mA A mA 35 1 10 10 88 40 100 100 112 dB A A % ns
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BSTH - DH = 4.5V, BSTL - DL = 4.5V, VOSENSE to VO VIDx < 2.4V VIDx < 2.4V
DH - PGNDH = 3.1V DH - PGNDH = 1.5v DL - PGNDL = 3.1V DL - PGNDL = 1.5V
1 100 1 100
2
SC1185 & SC1185A
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70C
Parameter Linear Sections Quiescent current Output Voltage LDO1 Output Voltage LDO2 Reference Voltage Gain (AOL) Load Regulation Line Regulation Output Impedance Gate Pulldown Impedance VOSENSE Impedance VGATE = 6.5V Iref < 100A LDOV = 12V
Conditions
Min
Typ
Max
Units
5 2.469 1.481 1.246 2.500 1.500 1.265 90 0.3 0.3 1 80 10 300 1.5 750 2.531 1.519 1.284
mA V V V dB % % k k
LDOS (1, 2) to GATE (1, 2) IO = 0 to 8A
GATE (1,2)-AGND; VCC=LDOV=OV
NOTE: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC1185 & SC1185A
POWER MANAGEMENT Pin Configuration
TOP VIEW
AGND GATE1 LDOS1 LDOS2 VCC REF PWRGOOD CSCS+ PGNDH DH PGNDL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GATE2 LDOV VID0 VID1 VID2 VID3 VID4 VOSENSE EN BSTH BSTL DL
Ordering Information
Part Number P ackag e
(1)
Linear Voltage
Temp Range (TJ) 0 to 125C
SC1185CSW.TR SC1185CSW.TRT(3) SC1185ACSW.TR SC1185ACSW.TRT(3) SO-24 1.5V2.5V 0 to 125C SO-24 1.5V2.5V
(24 Pin SOIC)
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name AGND GATE1 LDOS1 LSOS2 VCC REF PWRGOOD CSCS+ PGNDH DH PGNDL DL BSTL BSTH EN
(1) (1)
Notes: (1) Only available in tape and reel packaging. A reel contains 1000 devices. (2) SC1185A provides improved output tolerance. See Output Voltage Table. (3). Lead free product. This product is fully WEEE and RoHS compliant.
Pin Function
Small Signal Analog and Digital Ground Gate Drive Output LDO1 Sense Input for LDO1 Sense Input for LDO2 Input Voltage Buffered Reference Voltge output Open collector logic output, high if VO within 10% of setpoint Current Sense Input (negative) Current Sense Input (positive) Power Ground for High Side Switch High Side Driver Output Power Ground for Low Side Swtch Low side Driver Output Supply for Low Side Driver Supply for High Side Driver Logic low shuts down the converter. High or open for normal operation. Top end of internal feedback chain Programming Input (MSB) Programming Input Programming Input Programming Input Programming Input (LSB) +12V for LDO section Gate Drive Output LDO2
VOSENSE VID4 (1) VID3 (1) VID2 VID1 VID0
(1) (1) (1)
LDOV GATE2
Note: (1) All logic level inputs and outputs are open collector TTL compatible.
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SC1185 & SC1185A
POWER MANAGEMENT Block Diagram
CSCS+ VCC EN
CURRENT LIMIT
REF
BSTH
LEVEL SHIFT AND HIGH SIDE MOSFET DRIVE
R
70mV
+
VID4 VID3 VID2 VID1 VID0
DH
D/A
OSCILLATOR
S
Q
PGNDH
VOSENSE
SHOOT-THRU CONTROL
OPEN COLLECTORS
+
PWRGOOD
+ + -
+ -
BSTL
ERROR AMP
SYNCHRONOUS MOSFET DRIVE
DL
AGND
LDOS1 GATE1
PGNDL
1.5V FET CONTROLLER
AGND
2.5V FET CONTROLLER
1.265V REF
LDOV
REF
GATE2 LDOS2 AGND
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SC1185 & SC1185A
POWER MANAGEMENT Output Voltage Table
Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; = 0C < Tj < 85C
Parameter Vid 43210 Output Voltage 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 Min 1.277 1.326 1.375 1.424 1.478 1.527 1.576 1.625 1.675 1.724 1.782 1.832 1.881 1.931 1.980 2.030 1.970 2.069 2.167 2.266 2.364 2.463 2.561 2.660 2.758 2.842 2.940 3.038 3.136 3.234 3.332 3.430
Standard Typ 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000 2.050 2.000 2.100 2.200 2.300 2.400 2.500 2.600 2.700 2.800 2.900 3.000 3.100 3.200 3.300 3.400 3.500 Max 1.323 1.374 1.425 1.476 1.523 1.573 1.624 1.675 1.726 1.818 1.869 1.919 1.970 2.020 2.020 2.071 2.030 2.132 2.233 2.335 2.436 2.538 2.639 2.741 2.842 58 3.060 3.162 3.264 3.366 3.468 3.570 Min 1.287 1.337 1.386 1.436 1.485 1.535 1.584 1.634 1.683 1.733 1.782 1.832 1.881 1.931 1.980 2.030 1.970 2.069 2.167 2.266 2.364 2.463 2.561 2.660 2.758 2.842 2.940 3.038 3.136 3.234 3.332 3.430
"A" Version Typ 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000 2.050 2.000 2.100 2.200 2.300 2.400 2.500 2.600 2.700 2.800 2.900 3.000 3.100 3.200 3.300 3.400 3.500 Max 1.313 1.364 1.414 1.465 1.515 1.566 1.616 1.667 1.717 1.768 1.818 1.869 1.919 1.970 2.020 2.071 2.030 2.132 2.233 2.335 2.436 2.538 2.639 2.741 2.842 2.958 3.060 3.162 3.264 3.366 3.468 3.570 Units V
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SC1185 & SC1185A
POWER MANAGEMENT Layout Guidelines
Careful attention to layout requirements are necessary for successful implementation of the SC1185 PWM controller. High currents switching at 140kHz are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom FET ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Bottom FET (Q2) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically "cleaner" grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). The connection between the junction of Q1, Q2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. The connection between the output inductor and the sense resistor should be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length is not so important, however adding unnecessary impedance will reduce efficiency.
12V IN
5V
10 1 2 3 4 0.1uF 5 6 0.1uF 7 8 9 10 11 12
AGND GATE1 LDOS1 LDOS2 VCC REF PWRGOOD CSCS+ PGNDH DH PGNDL GATE2 LDOV VID0 VID1 VID2 VID3 VID4 VOSENSE EN BSTH BSTL DL
24 23 22 21 20 19 18 17 16 15 14 13 Q2 Cout L Q1 2.32k Cin + 1.00k 5mOhm Vout +
SC1185
Heavy lines indicate
3.3V Q3 + Cin Lin Cout Lin1 + Vo Lin1
high current paths. Layout Diagram SC1185(A)
Vo Lin2 Q4 Cout Lin2 +
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SC1185 & SC1185A
POWER MANAGEMENT Layout Guidelines
4) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC1185 is best placed over a quiet ground plane area, avoid pulse currents in the Cin, Q1, Q2 loop flowing in this area. PGNDH and PGNDL should be returned to the ground plane close to the package. The AGND pin should be connected to the ground side of (one of) the output capacitor(s). If this is not possible, the AGND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no circumstances should AGND be returned to a ground inside the Cin, Q1, Q2 loop. 6) Vcc for the SC1185 should be supplied from the 5V supply through a 10 resistor, the Vcc pin should be decoupled directly to AGND by a 0.1F ceramic capacitor, trace lengths should be as short as possible. 7) The Current Sense resistor and the divider across it should form as small a loop as possible, the traces running back to CS+ and CS- on the SC1185 should run parallel and close to each other. The 0.1F capacitor should be mounted as close to the CS+ and CS- pins as possible. 8) Ideally, the grounds for the two LDO sections should be returned to the ground side of (one of) the output capacitor(s).
5V
+
Vout +
Currents in various parts of the power section
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SC1185 & SC1185A
POWER MANAGEMENT Layout Guidelines
COMPONENT SELECTION WITCHING S WITCHING SECTION CAPACITORS OUTPUT CAPACITORS - Selection begins with the most critical component. Because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. Output capacitor ESR is therefore one of the most important criteria. The maximum ESR can be simply calculated from:
R ESR Where Vt = Maximum transient voltage excursion It = Transient current step Vt It
The calculated maximum inductor value assumes 100% and 0% duty cycle, so some allowance must be made. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. Note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from:
ILRIPPLE = VIN 4 L fOSC
For example, to meet a 100mV transient limit with a 10A load step, the output capacitor ESR must be less than 10m. To meet this kind of ESR level, there are three available capacitor technologies.
Each Cap. Technology C (F) 330 330 1500 ESR (m) 60 25 44 Total ESR (m) 10 8.3 8.3
Ripple current allowance will define the minimum permitted inductor value. POWER POWER FETS - The FETs are chosen based on several criteria with probably the most important being power dissipation and power handling capability. TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses. a) Conduction losses are simply calculated as:
2 PCOND = IO RDS(on)
Qty. Rqd. C (F) 6 3 5
Low ESR Tantalum OS-CON Low ESR Aluminum
2000 990 7500
The choice of which to use is simply a cost/performance issue, with Low ESR Aluminum being the cheapest, but taking up the most space. INDUCTOR INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above. The maximum inductor value may be calculated from:
L R ESR C VA It
where = duty cycle VO VIN
b) Switching losses can be estimated by assuming a switching time, if we assume 100ns then:
PSW = IO VIN 10 -2
or more generally,
PSW = IO VIN ( t r + t f ) fOSC 4
c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be:
PRR = QRR VIN fOSC
where VA is the lesser of VO or (VIN - VO )
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SC1185 & SC1185A
POWER MANAGEMENT Layout Guidelines
sider conduction losses to determine FET suitability. For a 5V in; 2.8V out at 14.2A requirement, typical FET losses would be: Using 1.5X Room temp RDS(ON) to allow for temperature rise.
FET type IRL34025 IRL2203 S i 4410 RDS(on) (m) 15 10.5 20 PD (W) 1.69 1.19 2.26 P a cka g e D 2P a k D 2P a k S0-8
position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4. CAPACITORS INPUT CAPACITORS - since the RMS ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size.
BOTT TTOM BOTTOM FET - Bottom FET losses are almost entirely due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it, resulting in low switching losses. Conduction losses for the FET can be determined by:
2 PCOND = IO RDS( on) (1 - )
For the example above: FET type IRL34025 IRL2203 Si4410 RDS(on) (m) 15 10.5 20 PD (W) 1.33 0.93 1.77 Package D2Pak D2Pak S0-8
Each of the package types has a characteristic thermal impedance, for the TO-220 package, thermal impedance is mostly determined by the heatsink used. For the surface mount packages on double sided FR4, 2 oz printed circuit board material, thermal impedances of 40oC/W for the D2PAK and 80oC/W for the SO-8 are readily achievable. The corresponding temperature rise is detailed below:
Temperature rise (oC) FET type IRL34025 IRL2203 S i 4410 Top FET 67.6 47.6 180.8 Bottom FET 53.2 37.2 141.6
It is apparent that single SO-8 Si4410 are not adequate for this application, but by using parallel pairs in each
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SC1185 & SC1185A
POWER MANAGEMENT Typical Characteristics
Typical Efficiency at Vo=3.5V
95% 95%
Typical Efficiency at Vo=2.8V
90%
90%
Efficiency
85% Efficiency 3.5V Std 3.5V Sync 3.5V Sync Lo Rds
85%
80%
80% 2.8V Std 2.8V Sync 2.8V Sync Lo Rds
75%
75%
70% 0 2 4 6 8 Io (Am ps) 10 12 14 16
70% 0 2 4 6 8 Io (Am ps) 10 12 14 16
Typical Efficiency at Vo=2.5V
95%
95%
Typical Efficiency at Vo=2.0V
90%
90%
Efficiency
Efficiency
85%
85%
80% 2.5V Std 2.5V Sync 2.5V Sync Lo Rds
80% 2.0V Std 2.0V Sync 2.0V Sync Lo Rds
75%
75%
70% 0 2 4 6 8 Io (Amps) 10 12 14 16
70% 0 2 4 6 8 Io (Am ps) 10 12 14 16
Typical Ripple, Vo=2.8V, Io=10A
Transient Response Vo=2.8V, Io=300mA to 10A
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TABLE VALID FOR 1x5mOhm SENSE RESISTOR +
VOUT
J1
12V C26 4.7uF
POWER MANAGEMENT Typical Application Circuit
J21
J16 R1 10 C18 1500uF + C19 1500uF + C1 0.1uF
5V
1 2 3 4
C2 1500uF
+
C3 1500uF
+
CON4 U3 5
VCC PWRGOOD VID0 VID1 VID2 VID3 VID4 EN AGND LDOV REF GATE1 LDOS1 GATE2 LDOS2 PGNDL PGNDH DL BSTL DH BSTH VOSENSE CSCS+
DROOP mV/A 0 1 2 5 1 2 5 1 2 5
OFFSET mV/V 0 2 2 2 5 5 5 10 10 10
R11 (Ohm) 0 2.5 3.3 EMPTY 6.3 8.3 EMPTY 12.5 16.7 EMPTY
R15 (Ohm) EMPTY 10 5 2 25 12.5 5 50 25 10
R3 C4 0.1uF 9 8 17 15 11 14 13 10 12 6 2 3 2 4 Q6 J13 J14
2.5V 1.5V
EMPTY 7 22 21 20 19 18 16 1 23 24 4 SC1185CS 3 8 + 12V Q4 IRLR3103N R10 2R2 L1 R15 See Table 2 1.9uH R11 See Table 2 C8 R12 1k C6 + Q3 IRLR3103N R9 2R2 R8 5mOhm Q1 IRLR3103 R6 2R2 R4 1.00k R5 2.32k Q2 IRLR3103N R7 2R2 0.1uF
C5
VID0
VID 43210 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000
VOUT VID 43210 1.30 11111 1.35 11110 1.40 11101 1.45 11100 1.50 11011 1.55 11010 1.60 11001 1.65 11000 1.70 10111 1.75 10110 1.80 10101 1.85 10100 1.90 10011 1.95 10010 2.00 10001 2.05 10000
NO CPU 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50
VID1
VID2
VCC_CORE + C9 C7 + + C10 0.1uF J17
1 2 3 4
VID3
12
U2A LM358 R16 0 R17 See Table R18 See Table 1 C14 330uF J23 J24 + C15 330uF C16 330uF C17 330uF + + + IRLR024N C13 0.1uF J25 J15
VID4
EN
654321
S1
1500uF 1500uF 1500uF 1500uF
CON4
J12
3.3V
3.3V
J18 SCOPE TP
C11 330uF
+
Q7 IRLR024N VLIN3 + C24 330uF +
C20 + J19 C22 +
C21 + C23 +
+
C12 330uF
Q5 IRLR024N
C25 330uF J20
VLIN3 1.5V 1.8V 2.5V R17 18.7 42.2 97.6
1500uF 1500uF 1500uF 1500uF
R18 100 100 100
J22
SC1185 & SC1185A
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SC1185 & SC1185A
POWER MANAGEMENT Materials List
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Qty. 5 12 8 1 1 4 3 1 1 1 1 4 1 2 1 1 2 1 1 Reference C1, C4, C5, C10, C13 C2, C3, C6, C7, C8, C9, C18, C19, C20, C21, C22, C23 C11, C12, C14, C15, C16, C17, C24, C25 C26 L1 Q1, Q2, Q3, Q4 Q5, Q6, Q7 R1 R3 R4 R5 R6, R7, R9, R10 R8 R15, R11 R12 R16 R17, R18 U2 U3 Value 0.1uF Ceramic 1500uF 330uF 4.7uF 1.9uH IRLR3103N IRLR024N 10 EMPTY 1.00k 2.32k 2R2 5mOhm See Table 1k 0 See Table LM358 SC1185CS SEMTECH IRC OAR-1 Series 6 Turns 16AWG on MICROMETALS T50-52D core Sanyo MV-GX or equiv. Low ESR Notes
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SC1185 & SC1185A
POWER MANAGEMENT Outline Drawing - SO - 24
A
N
e
D
DIM
A A1 A2 b c D E1 E e h J L L1 N R 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
2.65 .104 2.35 .093 0.30 .012 0.10 .004 2.55 .100 2.05 .081 .012 .020 0.31 0.51 0.33 .013 0.20 .008 .602 .606 .610 15.30 15.40 15.50 .291 .295 .299 7.40 7.50 7.60 .406 BSC 10.30 BSC .050 BSC 1.27 BSC .010 .030 0.25 0.75 .020 .030 0.50 0.75 1.04 .041 0.40 .016 (1.04) (.041) 24 24 .024 .035 0.60 0.90 8 0 8 0 0.10 .004 0.25 .010 0.33 .013
2X E/2
E1 R
E
ccc C
2X N/2 TIPS
1
2
3
e/2 B
D
aaa C SEATING PLANE C J
h A2 A H bxN bbb A1 C A-B D GAGE PLANE 0.25 SEE DETAIL L (L1) DETAIL c h
01
NOTES: 1. 2. 3. 4.
SIDE VIEW
A
A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -HDIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. REFERENCE JEDEC STD MS-013, VARIATION AD.
Land Pattern - SO - 24
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.362) .276 .050 .024 .087 .449 (9.20) 7.00 1.27 0.60 2.20 11.40
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 307A.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012-8790 Phone: (805)498-2111 FAX (805)498-3804
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